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CoverageMaster winAMS FAQ
MPU Specific Issues
114_04: Using an ARM Cortex MPU, running tests for a function
calling a sub-function through a function pointer does not execute
correctly. How do I fix it?
Question:
I am using an ARM Cortex MPU and I want to test a function that calls a sub-function through a function pointer. I have set the function name to be called by function pointer in the test CSV file. During simulation, the sub-function is called, but an error occurs during the called function's execution, or it does not return to the test function. How do I fix it?
Answer:
This occurs due to interworking between ARM and Thumb states in the program. If the sub-function is called with a BX or BLX instruction, the processor changes modes according to the LSB of the branch address:
if bit 0 is set, the instructions at the branch
address are executed in Thumb state,
if bit 0 is clear, the instructions at the branch
address are executed in ARM state.
The LSB is then evaluated as 0 for the actual address to jump to.
Note: Bit 0 of an address can be used in this way because:
all ARM instructions are word-aligned, so bits 0 and 1
of the address of any ARM instruction are unused,
all Thumb instructions are halfword-aligned, so bit 0 of
the address of any Thumb instruction is unused.
Consequently, when setting function pointers in a CSV file, modify the last bit of the pointer according to which mode the sub-function is compiled in (0 for ARM mode, 1 for Thumb mode).
Example:
//source1.c, compiled in ARM Mode
int add(int num1, int num2) {
return ( num1 + num2 );
}
//source2.c, compiled in THUMB Mode
int sub(int num1, int num2) {
return ( num1 - num2 );
}
int (*pfunc[2]) (int num1, int num2);
int test_func(int num1, int num2){
int ret;
ret = 0;
ret = ret + (*pfunc[0])(num1, num2);
ret = ret + (*pfunc[1])(num1, num2);
return ret;
}
//Test CSV:
#COMMENT| @num1 | @num2 | pfunc[0] | pfunc[1] | @@test_func
--------------+----------+----------+-----------+--------------+------------------
| 1 | 1 | add |
sub+1 | 2
Reference: See ARM’s documentation for additional details
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