News
- 2024/12/09
- NEWS
Product Version Update Information (CMW RISC-V)
Thank you for using Gaio Technology products.
The following Product Update has taken place.
The following Product Update has taken place.
Update Information
[Product name]
CoverageMaster winAMS
[Affected MPUs]
Simulator Engine : SX(High Speed)
RISC-V(RV32)
RISC-V(RV64)
CoverageMaster winAMS
[Affected MPUs]
Simulator Engine : SX(High Speed)
RISC-V(RV32)
RISC-V(RV64)
Update Contents
RISC-V(RV32)Processor Model hsnwt1 : V1.03.0
Functional Improvements (For RISC-V RV32)
• Zc* Extended Instructions (zca/zcb/zcf/zcd/zcmp/zcmt/zce) implemented.
Extended Instructions can be used with the command "DIRECT ENABLE ZCA/ZCB/ZCF/ZCD/ZCMP/ZCMT/ZCE"
• zicond Extended Instructions implemented.
Extended Instructions can be used with the command "DIRECT ENABLE ZICOND"
• For the non-implemented svinval/zawrs/h Extended Instructions, the command "DIRECT ERROR/NOP SVINVAL/ZAWRS/H" has been added to implement Error Termination or NOP operation.
• The EBREAK/C.EBREAK Instructions were implementing NOP operation but now default to Error Termination.
Also, a "DIRECT ERROR/NOP EBREAK" command has been added to allow selection of Error Termination or NOP operation.
• CSR (Control and Status Register) Read/Write has been enabled for the following Extended Instructions:
Machine ISA・Supervisor ISA/Sstc/Ssaia/Smaia/Sscofpmf/Smstateen/Ssstateen/Zicntr/Zihpm
The command "DIRECT ENABLE ZICSR" must be executed to enable this.
Extended Instructions can be used with the command "DIRECT ENABLE ZCA/ZCB/ZCF/ZCD/ZCMP/ZCMT/ZCE"
• zicond Extended Instructions implemented.
Extended Instructions can be used with the command "DIRECT ENABLE ZICOND"
• For the non-implemented svinval/zawrs/h Extended Instructions, the command "DIRECT ERROR/NOP SVINVAL/ZAWRS/H" has been added to implement Error Termination or NOP operation.
• The EBREAK/C.EBREAK Instructions were implementing NOP operation but now default to Error Termination.
Also, a "DIRECT ERROR/NOP EBREAK" command has been added to allow selection of Error Termination or NOP operation.
• CSR (Control and Status Register) Read/Write has been enabled for the following Extended Instructions:
Machine ISA・Supervisor ISA/Sstc/Ssaia/Smaia/Sscofpmf/Smstateen/Ssstateen/Zicntr/Zihpm
The command "DIRECT ENABLE ZICSR" must be executed to enable this.
OMF Converter RiscvGccOmf : V1.3.0.0
Compiler Version Implementation
• The following Compilers have been implemented.
GNU Compiler（riscv-none-elf-gcc.exe） V14.2.0
GNU Compiler（riscv-none-elf-gcc.exe） V14.2.0
Functional Improvements
• Coverage Measurement Results for unused code have been improved.
For consistency with previously obtained Coverage Results, use the option omfc_line_compat_1201 in the Coverage Master winAMS settings.
For consistency with previously obtained Coverage Results, use the option omfc_line_compat_1201 in the Coverage Master winAMS settings.
