News
- 2023/09/25
- NEWS
Product Version Update Information (CMW RISC-V (RV32/RV64) )
Thank you for using Gaio Technology products.
The following Product Update has taken place.
The following Product Update has taken place.
Update Information
[Product name]
Coverage Master winAMS
[Product Version]
Simulator Engine: SX (High Speed)
RISC-V (RV32)
RISC-V (RV64)
Coverage Master winAMS
[Product Version]
Simulator Engine: SX (High Speed)
RISC-V (RV32)
RISC-V (RV64)
Update Contents
RISC-V (RV32) Processor Model hsnwt1 : V1.02.1
RISC-V (RV32) Reverse Assembler duawt1 : V1.2.0.1
Functional Improvements
• Implementation of Bit Operation Expanded Instructions (Zba/Zbb/Zbc/Zbs)
• DIRECT ENABLE/DISABLE/SHOW NAN_BOXING Commands added which check NanBoxing for single precision floating point instructions.
• DIRECT ENABLE/DISABLE/SHOW NAN_BOXING Commands added which check NanBoxing for single precision floating point instructions.
OMF Converter RiscvGccOmf : V1.2.0.1
Target Compiler: GNU Compiler (riscv32-unknown-elf-gcc)
Implemented Compiler Version
• GNU Compiler (riscv32-unknown-elf-gcc) V12.2.0 is implemented.
RISC-V (RV64) Processor Model hsnwq1 : V1.01.1
RISC-V (RV64) Reverse Assembler duawq1 : V1.1.0.1
New Processor Models implemented
• RISC-V (RV64) Processor Model hsnwq1 : V1.01.1
• RISC-V (RV64) Reverse Assembler duawq1 : V1.1.0.1
• RISC-V (RV64) Reverse Assembler duawq1 : V1.1.0.1
OMF Converter RiscvGccOmf : V1.2.0.1
Target Compiler : GNUCompiler (riscv64-unknown-linux-gnu-gcc)
New Compiler Implemented
• GNUCompiler (riscv64-unknown-linux-gnu-gcc) V12.2.0 is newly implemented.
